A friendly guide to a circuit that slows a clock, the computer experiments behind a paper draft, and the questions the evidence cannot yet answer.
Read this first. This is a draft study. Its circuit results are simulation-only and pre-layout (computer tests without a finished physical chip design). Nothing has been submitted for publication. No silicon or FPGA hardware result is claimed.
First, here is the story without assuming you know circuit design. All circuit results below are computer simulations, before a finished physical layout.
The whole story in 60 seconds
A clock is a repeating electrical beat, and a divider makes a slower beat from it. This circuit also makes eight versions of that slower beat, ideally spaced evenly like runners on a track. We took a published design and tested it in a newer chip-making process. It could keep the slower beat, but its timing signals were often unevenly spaced. The settings that made the spacing most even were close to where the circuit stopped working reliably. We rewrote the paper to explain this trade-off and show what the saved evidence can actually support.
Analogies in one glance
DividerA gearbox that halves a clock’s speed.
Eight phasesEight runners spaced evenly around a track; each marks a different moment in the repeating beat.
The pair effectRunners start in twos, so gaps alternate long and short instead of being even.
PVT cornersTesting in hot and cold weather, on weak and strong batteries, and with good and bad factory batches: 45 selected combinations of process, voltage and temperature.
MismatchEven identical twins are never exactly identical; matching parts in a circuit can differ a little too.
Monte CarloBuilding 200 slightly different copies on a computer to see how modeled differences affect them.
Pre-registrationWriting down a prediction before running an experiment so the goalposts cannot be moved afterward.
AuditA second person checks the numbers and how they were obtained.
What we did to the paper, in order
First draft and independent checks. The draft tried to sell a simple rule that explained everything. Independent checks found that several claims were stronger than the evidence, so we narrowed them.
A better question. We stopped framing this as a new divider. Instead we asked whether the published design still works in a modern 45 nm chip process, and how accurately its eight timing phases are spaced versus how reliably it divides.
A wrong claim removed. We thought the speed limit and the condition for even spacing coincided. Rechecking showed that the predicted conditions differ by a factor of two, so we dropped the claim.
Predictions written down first. In E3 we guessed how large the load resistor, a part that limits current, must be for division to start. The guess matched the onset in all 10 tested conditions, although 4 of 110 simulated runs divided slightly below it. In E6 we predicted where the timing phases would become perfectly even; in the tested range they never did before division failed. Simulation, Level S: E3 and E6 summaries and protocols.
Why pairs appear. We explained the alternating gaps using the delay through one latch, a tiny circuit that holds a state. If x is the short gap in the nominal model, the error from the ideal spacing is |45° − x|: the distance between the short gap and the perfect gap. Mismatch can break this simple pattern. Simulation, Level R: retained nominal waveforms.
Stress tests and imperfect copies. Across 45 weather, battery and factory combinations and experiments with 200 modeled copies, design D generally kept dividing but was never phase-accurate under the tested conditions; its nominal error was 38.5°, and its best dividing corner error was 29.8°. At its nominal 6 GHz input, design B had 3.78° error, but divided in only 21 of 45 selected corners and only 1 of 200 mismatch-only copies. The paired pattern breaks under mismatch. Degrees describe timing around one full cycle; GHz means billions of clock cycles per second. Simulation: nominal D and B Level R; corner and mismatch summaries Level S.
A finer speed scan. E7 sampled more input speeds near the stopping point. Its best sampled accuracy improved from 3.78° to 1.71° at 6.05 GHz; in every tested scan the short gap stayed below the perfect 45° before division stopped. This is a sampled result, not a guarantee between samples. Simulation, Level S: E7 summary.
Reviews and a correction. Audits and peer reviews first said no-go. A fix pass went too far and deleted 22 results, so we restored them and labelled results by evidence level: R means recomputed from saved waveforms, the original signal traces; S means calculated from saved summary tables that can be checked again, without the individual traces.
Putting context back. We restored the paragraph about related work with web-checked references, fixed overlapping figure labels, and began a plain-language rewrite with the authors’ names; a second-author placeholder remains.
Where it stands. The result is a four-page paper plus references. An earlier review gave soundness 3/5, novelty 2/5, significance 2/5 and clarity 4/5, and suggested a weak accept at a student or regional conference if framed as a careful negative-result study. These are opinions, not acceptance odds. Nothing has been submitted.
What is new in ours (and what is not)
New in this study
Copying the published sizing rule directly into the 45 nm model did not make the circuit divide; it buzzed at the wrong frequency with a tiny signal swing.
A simple estimate based on counting stacked transistors predicted the load needed to start dividing, and was tested after the prediction was written down.
The pair explanation and formula describe why the nominal timing signals are unevenly spaced.
The tested trade-off between phase accuracy and reliable division is quantified across 45 selected conditions and 200 modeled mismatch copies.
Paper numbers are tied to re-runnable checks in a register of about 1,200 checked values; results are labelled R or S by evidence level.
Not new or not claimed
The circuit itself is the published design.
No chip was built; there is no result extracted from a completed layout or measured on silicon.
The study uses one process kit and an ideal clock.
The estimate is not a general design rule.
This is not a claim of a better divider: the original is measured silicon at 180 nm, ours is simulated at 45 nm, and the numbers are not a ranking.
Why this is still useful
Knowing where a promising design struggles can save the next researcher time. The paired-runner explanation helps show why a circuit can divide correctly yet produce uneven timing. The documented checks also make clear which conclusions can be retraced and which need stronger evidence.
Use these questions to test the boundaries of the draft. Search filters the questions and answers as you type.
Novelty and context
What is new compared with the published design and other dividers?
We studied an existing circuit in a different chip-making process. The circuit is inherited. This work characterizes process transfer, paired steps, corners and mismatch; the novelty search is limited to the recorded queries. Source: NICHE_DECISION.md.
Is this a new circuit or general design law?
No, we did not invent a new circuit or a rule for every design. No. It is a process-specific characterization and an empirical heuristic. Source: manuscript_v2.tex.
Are the comparison results a ranking?
No, the two studies cannot be ranked fairly. No. The original paper reports measured silicon; this study uses a different process and supply in pre-layout simulation, with different measurement definitions. Source: peer_review_v2_r2.md.
Validity and method
Is the divider physically demonstrated?
No, the result comes from computer models. No silicon measurement, extracted layout or layout-versus-schematic clean result is shown. Source: manuscript_v2.tex.
What simulation assumptions matter?
The clock and connected parts are simplified in the model. The testbench uses an ideal clock, fixed loads and plain Spectre resistors. Sensitivity to these assumptions is not shown. Source: peer_review_v2_r2.md.
Why these process, voltage and temperature corners?
They are stress tests, not a prediction of factory output. The grid combines the selected process, temperature and supply settings to probe deterministic extremes; it is a coverage choice, not a probability model. Source: joint_spec.py.
Why was the Monte Carlo sample count chosen?
The team chose a practical sample size, but did not show a formal justification. The protocol used a finite practical sample count; a statistical power justification is not shown. Source: mc_stats.py.
What do Level R and Level S mean?
They tell you how far back the saved evidence goes. R means a result re-derived from retained nominal raw waveforms; S means an archived scripted-flow summary without the individual campaign waveforms. Source: fix_log_v2b.md.
Why are campaign waveforms missing?
The individual traces were not saved in the repository. They were not retained in the repository; the records do not establish a scientific reason for that choice. E7 raw archives remain in the simulation environment. Source: e7_register_notes.md.
Are corner pass counts yield?
No, these selected tests do not tell us the share of chips that would work. No. Corners are selected deterministic settings, not a probability-weighted population of fabricated devices. Source: manuscript_v2.tex.
How is phase-step error defined?
It measures the biggest uneven gap between neighboring timing signals. Sort output rising-edge phases around a full cycle, include the wraparound gap, and take the largest absolute deviation from equal spacing. Source: manuscript_v2.tex.
How is division judged?
The test checks that every output keeps the expected slower beat. A strict checker compares output periods and edge counts across every output with the expected divided clock. Source: manuscript_v2.tex.
Results and generalisation
Why can D divide but fail phase accuracy?
Keeping the beat and spacing the beats evenly are different jobs. Division checks periodic behavior; a separate phase check exposes uneven spacing. Source: joint_spec.py and phase_mechanism.py.
Why does B pass the strict corner test only at one sampled point?
The promising setting sits close to where division stops working. Its nominal pair spacing approaches equal spacing near loss of division. The sampled grid does not establish a robust continuous operating band. Source: peer_review_v2_r2.md.
What does the E7 refinement show?
A finer scan found a more accurate sampled setting near the stopping point. The best reported last-dividing sample is a small maximum phase-step error for B near the division cliff. This is a nominal summary-backed result, not a robustness demonstration. Source: cliff_summary.tsv.
Why does mismatch disturb the paired description?
Small differences between devices can disturb the paired rhythm. Unequal device parameters introduce multiple timing differences, so the single nominal delay separation no longer describes every step. Source: NICHE_DECISION.md.
Is the last observed short step a bound?
No, the tested points do not prove a limit for every circuit. No. Its variation across the tested series does not establish a universal bound. Source: e7_register_notes.md.
Does the stack estimate work at other nodes?
We do not know whether it works in other processes. Not shown; only the tested kit and settings support this empirical estimate. Source: E3_PROTOCOL.md.
Is the stack expression a regeneration condition?
No, it is a useful guess rather than a proof of startup. No. It is an empirical onset heuristic, not a derived sufficient condition for regeneration. Source: RULINGS_V2R.md.
What about duty cycle, output load and startup?
Those effects need further testing. A sensitivity matrix for these factors is not shown. Fixed testbench assumptions limit generalization. Source: peer_review_v2_r2.md.
Does Monte Carlo establish manufactured yield?
No, computer variations are not a measurement of factory yield. No. It samples the available device models under the specified testbench; it does not validate fabrication yield. Source: manuscript_v2.tex.
Reproducibility, ethics and venues
Can someone trace a number?
Yes, the register points to the evidence and calculation. The claims register associates each manuscript claim with evidence and a rerun command. It is a map, not a substitute for missing waveforms. Source: claims_register.csv.
Could every result be independently re-derived?
Not all the way back to original traces for every campaign. No. Summary-backed campaigns cannot be independently recovered from their individual raw waveforms in the repository. Source: rederive_v2.md.
Were reviews independent of the writer?
Separate reviews were recorded; their reports describe the checks. The project recorded separate numerical, prose and layout audits and peer reviews; see the review files for findings and responses. Source: numbers_audit_v2.md, prose_audit_v2.md, layout_audit_v2.md.
Was artificial intelligence used?
The authors remain responsible for the paper and any required disclosure. The analysis scripts and audits are reproducible where the evidence exists; authors remain responsible for the work and any disclosure required by a venue. Source: PROGRESS.md.
Why consider a preprint and IEEE Access?
They were considered as possible ways to share the work. The decision log records a preference for a public preprint followed by a broad journal; suitability and any publication fee still require verification. Source: DECISIONS.md.
Why not RFIC, MWTL or TCAS-II?
Reviewers saw limits that make selective circuits venues a difficult fit. The review found the inherited circuit, missing physical validation and limited generality weak for a selective circuits venue. A venue decision remains human. Source: peer_review_v2.md.
What should be done next?
The next step is to test the assumptions and eventually physical hardware. Test clock duty, load and startup sensitivity; complete physical layout and extraction; then consider silicon. None is established by this draft. Source: peer_review_v2_r2.md.
Has anything been submitted?
No, nothing has been submitted. No submission is claimed. The venue plan is a proposal, not acceptance. Source: DECISIONS.md.
What does the FPGA demonstration prove?
It demonstrates a simplified digital timing idea. It illustrates digital timing behavior; no connected board or programmed hardware result is claimed, and it is not the analog CMOS circuit. Source: FPGA README.
Can an error-free checker recreate missing evidence?
No, a calculation cannot bring back a missing trace. No. A successful check against a summary validates arithmetic on that summary; it cannot recover an unarchived waveform. Source: rederive_v2.md.
Is the reference edge-balance equation a failure of the original work?
No, the original formula had a different purpose. No. It was designed for rise/fall balance in its original context; transferring it unchanged is a separate experiment. Source: RULINGS_V2R.md.
What is the most important uncertainty?
We do not yet know whether a physical chip would behave like the model. The model-specific behavior has not been tested against extracted parasitics or fabricated devices. Source: manuscript_v2.tex.
Are the reviewer scores acceptance probabilities?
No, the scores are opinions, not odds of acceptance. No. They are qualitative ratings from one review and cannot predict an editorial decision. Source: peer_review_v2_r2.md.
FPGA (digital emulation)
Why use a digital FPGA for this?
It is a simplified digital model, not the analog circuit. To act out simplified timing of the pair mechanism on a model train scale. It is a digital synchronous model, not an analog CMOS emulator. Source: FPGA README.
Does the FPGA validate the analog Spectre results?
No, it cannot validate the analog Spectre results. No. It cannot validate transistor-level behavior, regeneration, GHz operation, or analog power/jitter. It only supports quantized pair bookkeeping. Source: FPGA README and run02_README.md.
Why do 4 MHz reports not satisfy exact pairing?
Because of discrete 12/13 tick quantization at 4 MHz. The model uses discrete 12/13 tick alternating half periods at 4 MHz rather than ideal 12.5 ticks, so the quantized timing produces alternation that is not exactly equal. Source: FPGA README.
Why no scope/external pin measurement?
Because only internal telemetry was measured with the same clock. All telemetry is internal FPGA cycle counters received over UART with the same clock generating and recording; external output-pin timing was not measured. Source: FPGA README.
What is the cycle-accurate oracle?
It is a tick-by-tick RTL replication that matched every report. A Python tick-by-tick replication of pair_emulator.v and edge_capture.v that reproduced every report bit-exactly across 99,848 valid reports with zero field mismatches. Source: run02_README.md and run02_cycle_oracle_results.json.
What would real validation need?
It would need external analog measurements independent of the model. External measurement (scope) of the analog circuit or extracted layout, testing at GHz with proper analog instrumentation, and verification independent of the same clock and model assumptions. Source: FPGA README and limits.
What is a frequency divider?
A clock is a repeating electrical timing signal. Its frequency tells us how many cycles occur per second; phase tells us where an edge sits within a cycle. A frequency divider produces an output that repeats more slowly than its input.
A multiphase divider also supplies several shifted versions of the output. A phased array uses phase relationships to steer a radio beam; a mixer combines signals to move information between frequencies; an interleaved analog-to-digital converter (ADC) staggers sampling among channels. In each, timing errors can matter.
For equal output spacing, divide a full turn into equal slices. Uneven steps mean neighboring edges are not evenly distributed even if each output has the right frequency.
A simplified timing picture: adjacent phase steps come in pairs in the nominal symmetric model. Source: phase_mechanism.py.
Clock. A periodic input controls when latches can update. Latches. Each latch stores a state and passes it onward; feedback closes the ring. Outputs. Each differential latch supplies a signal and its complement: Q1, Q2, Q3, Q4 and their complements Q1̅, Q2̅, Q3̅, Q4̅. The ideal equally spaced phase positions are 0°, 45°, 90°, 135°, 180°, 225°, 270° and 315°, measured relative to an arbitrary reference; the actual edge positions need not equal those targets. Source: phase_mechanism.py. Pair. A short interval and its neighboring long interval form a repeating pattern in the nominal model; physical mismatch can spoil that simplification.
The reference paper
The original authors describe a latch-ring multiphase divide-by-two circuit in IEEE Microwave and Wireless Technology Letters (2025), “A Compact Multiphase Divide-by-Two CMOS Frequency Divider,” DOI 10.1109/LMWT.2025.3528863. Source: refs.bib. The ring reuses latch states to generate multiple clock phases. The published load relation targets balanced rising and falling edges in its model; it is not a proof that the transferred circuit will regenerate or divide. The reference is measured silicon; this project uses a separate simulated process and is not a performance ranking. Source: manuscript_v2.tex; RULINGS_V2R.md.
The first project
The earlier student project reproduced the idea in Cadence using the GPDK045 process design kit (PDK), a modeled 45 nm process [simulation]. A current-mode logic (CML) D-latch steers current between differential branches; four latches form the ring. Source: manuscript_v2.tex; claims_register.csv.
Design D uses m = 4, R = 3 kΩ at 1.4 GHz input and 700 MHz output; Design B uses m = 4, R = 2 kΩ at 6 GHz input and 3 GHz output [simulation]. Bias trimming changes the operating point. Source: claims_register.csv; D_1p4.tsv; B_6g.tsv.
For D, standalone netlist power is 0.5413 mW [simulation, Level R]; Virtuoso schematic netlist power is 0.4554 mW [simulation, Level S]. Layout-dependent device parameters in the schematic-generated netlist account for the observed difference in the comparison; the comparison waveforms were not archived. These are distinct netlist variants, not post-layout power. Source: power_gap_experiment.md; claims_register.csv.
The layout is placement-only, with 21 DRC errors across 3 rules; no LVS-clean or extracted result is established. Source: assura_drc_dlatch_summary.txt; manuscript_v2.tex.
Swipe sideways to inspect the figure at readable size.
Retained nominal transient waveforms show why correct division does not guarantee evenly spaced phases. [simulation] Source: fig_v2_waveforms.png
The research story
The study moves from a published circuit to bounded simulation evidence and a draft.
Reference paper. The published circuit is the starting point.
Reproduce in GPDK045. A process design kit supplies transistor models to the circuit simulator.
Size designs D and B. Device size, load resistance and bias define the selected operating points.
Process, voltage, temperature. A corner grid changes process, supply and temperature.
Research question. The useful question became whether dividing and accurate spacing coexist.
Preregister E3 and E6. The protocols fixed a test before its results were interpreted.
Explain paired phase steps. Edge timing provides a compact description of nominal phases.
Test mismatch statistically. Monte Carlo introduces statistical variation into model parameters.
Map the division cliff. A refined frequency sweep examines the last observed dividing points.
Audit and revise. Independent reviewers checked numbers, prose and page layout.
Draft paper. The manuscript retains results with their evidence limitations.
Consider publication venues. A preprint and journal are possible future steps, not completed submissions.
The question is not simply “does it toggle?” It is whether this inherited ring can both divide and provide useful phase spacing under the tested conditions. E3 preregistered an empirical load-onset test; E6 preregistered a test of whether a low-frequency delay estimate reaches equal phase spacing within the observed dividing range. E3 supported its onset criterion in 10 of 10 tested size–bias conditions, while 4 of 110 individual runs divided below its threshold [simulation, Level S]. E6 found the predicted equal-spacing point beyond the observed dividing range in the tested dividing configurations. Neither establishes a universal rule. Source: E3_PROTOCOL.md; E6_PROTOCOL.md; e3_boundary.tsv; e6_grid.tsv; claims_register.csv.
Why paired steps?
Imagine people walking in pairs around a track: a delay inside each pair makes a short gap and a long gap. In the nominal symmetric ring, the neighboring angular gaps alternate between 90° − x and x. If the extra latch delay is δ and input frequency is fin, the nominal description is x = 180° δ fin and E = |45° − x|, where E is the maximum phase-step error. This relationship describes the retained nominal waveforms, not every mismatch sample. Source: phase_mechanism.py; manuscript_v2.tex.
Derive the phase relation
The output period is twice the input period. A time separation δ therefore occupies δ/(2Tin) of an output cycle. Multiplying by a full turn gives x = 180° δ/Tin. The paired gaps sum to a quarter turn, so their deviations from the equal step have the same magnitude. This relies on the nominal symmetric timing picture. Source: manuscript_v2.tex.
A simplified timing picture: adjacent phase steps come in pairs in the nominal symmetric model. Source: phase_mechanism.py.
Clock. A periodic input controls when latches can update. Latches. Each latch stores a state and passes it onward; feedback closes the ring. Outputs. Each differential latch supplies a signal and its complement: Q1, Q2, Q3, Q4 and their complements Q1̅, Q2̅, Q3̅, Q4̅. The ideal equally spaced phase positions are 0°, 45°, 90°, 135°, 180°, 225°, 270° and 315°, measured relative to an arbitrary reference; the actual edge positions need not equal those targets. Source: phase_mechanism.py. Pair. A short interval and its neighboring long interval form a repeating pattern in the nominal model; physical mismatch can spoil that simplification.
The corner grid is a deterministic stress test, not a manufacturing probability distribution. Source: joint_spec.py.
Process. Model corners represent device variations. Temperature and supply. Each setting is combined with each process model. Pass. The strict joint test requires division, sufficient swing and phase error within the illustrative 5° threshold. D passes 0 of 45 and B 1 of 45 [simulation, Level S]. Counting the corners that merely divide answers a different question. Source: pvt_D.tsv; pvt_B6.tsv; joint_spec.py.
Variation and the cliff
Monte Carlo samples modeled process and device mismatch; the principal campaigns use N = 200 samples [simulation, Level S]. This is not measured silicon yield. Plain resistors remain fixed, and the nominal pair description does not generally survive process-plus-mismatch. Source: mc_stats.py; manuscript_v2.tex.
E7 refines selected frequency sweeps near the loss of division. The refined bracket is 6.05 GHz dividing / 6.10 GHz failing, so the margin is about 0.05-0.1 GHz, not 0.2 GHz. Its best last-dividing Design B sample has 1.71° maximum phase-step error at 6.05 GHz [simulation, Level S]. It is a sampled nominal result, not a guaranteed band, physical measurement, or universal limit. The E7 summary is archived; its per-run raw archives are outside the repository. Source: cliff_summary.tsv; e7_register_notes.md; claims_register.csv.
Swipe sideways to inspect the figure at readable size.
Functional division and a stricter combined phase and swing requirement answer different questions. [simulation, Level S] Source: fig_v2_joint_spec.png
Decisions we took and why
The project changed its claims and presentation when reviews exposed missing support. Source: DECISIONS.md; NICHE_DECISION.md.
Thesis. The team chose process transfer and phase-versus-division margin over claiming a new circuit. Coincides. Re-derivation showed the proposed equal-phase and speed-limit conditions differ, so the claim was dropped. Evidence labels. An overly aggressive fix removed too much; the later decision retained bounded findings while marking waveform-backed R and summary-backed S evidence. Page budget. An earlier conference plan targeted four pages; the later journal strategy changed the constraint. Venue. The decision log favors a preprint then IEEE Access, subject to human approval and venue requirements. Source: RULINGS_V2R.md; NICHE_DECISION.md; DECISIONS.md.
What went wrong and how it was addressed
A limit claim was based on a false equivalence; the conditions were re-derived and the claim removed.
A fix pass cut too much evidence; results were restored with explicit provenance labels.
Automation quota limits interrupted work; the team rerouted tasks and recorded the interruption.
Simulation-host disk exhaustion interrupted work; storage was reorganized and recovery recorded.
The chain links an assertion back to its source; missing raw files limit how far the loop can go.
Netlist and simulator. The netlist defines the modeled circuit and testbench; Spectre computes a transient waveform. Waveform and measurement. Scripts extract edges, periods, swing and power. Summary. A TSV stores per-run measurements. Register. Each claim has a source and rerun command. Paper. Authors use registered values and audits check presentation. Loop. Rerunning summary arithmetic does not recreate unarchived raw waveforms. Source: claims_register.csv; rederive_v2.md.
Separate audits cover numbers and cross-references, prose and terminology, and layout. The earlier round-two review rated soundness 3/5, novelty 2/5, significance 2/5, and clarity 4/5; these are subjective reviewer scores. The other requested independent review reports that it was not performed, and gives no scores. Source: peer_review_v2_r2.md; peer_review_v2_sol.md; numbers_audit_v2.md; prose_audit_v2.md; layout_audit_v2.md.
Where the paper is going
The decision log proposes arXiv first, then IEEE Access. IEEE Access confirms that an article processing charge applies to accepted articles; the amount and any applicable discounts or taxes should be checked with the publisher before a decision. Source: IEEE Access Article Processing Charges page, checked 2 November 2026. An earlier option was ISQED, with a recorded deadline of 17 November 2026; the organizer’s call for papers also lists this as its final deadline, at midnight US Pacific time; check the live call for changes before acting. Source: ISQED Call for Papers, checked 2 November 2026. Nothing has been submitted. Source: DECISIONS.md; NICHE_DECISION.md.
The Basys 3 FPGA path
The FPGA path is a digital teaching demonstration, not a physical analog-divider measurement.
Model. An ideal-latch demo and a digital emulator model selected behavior. Flow. An open-source build flow and runbook describe how to prepare the design. Board. Basys 3 is the intended target. Evidence. No connected board, programmed device or hardware bitstream result is claimed here. A digital emulation cannot validate transistor-level analog operation. Source: FPGA README and EMULATOR_BUILD_ISSUES.md; PROGRESS.md.
What the FPGA board did, and what it did not do
A Basys 3 FPGA ran a digital 100 MHz-tick model of the pair mechanism (not the analog circuit, not GHz, not evidence for the Spectre results).
Run 01: 128 settings, 3 sweeps, 9,401 reports, max difference from the formula 3.6 degrees (within the one-tick bound). At nominal 4 MHz the alternating half periods were 12 and 13 ticks rather than the ideal 12.5 ticks, so exact continuous-time alternation is not satisfied.
Run 02: 10-minute soak and a cycle-accurate Python oracle that reproduces every report. The oracle is a tick-by-tick replication of the RTL (pair_emulator.v and edge_capture.v); across both runs all 99,848 valid reports matched bit-exactly with zero mismatches in k, f, the eight signed gaps s0..s7, E, and PRED. Two non-matching lines were physically accounted for as buffer residue and a JTAG reset collision during SRAM reconfiguration. The board has now been removed from the system.
What it did and did not do: The digital model supports the quantized pair bookkeeping only. It does not provide external pin measurements, does not run at GHz, uses the same clock to generate and record telemetry, and cannot validate transistor-level analog operation, regeneration, or Spectre results.
From a local checkout, use the project’s documented checks and the exact rerun command in the relevant row of claims_register.csv. Commands below check the archived project; they do not produce missing raw waveforms or require a new simulation.
make help
make check
The register points to the checker for each number; the E7 checker can recalculate its summary-backed result, while the raw recomputation script works on the retained nominal waveform files. The earlier project also includes desktop launchers for project folders, the v1 report and v2 paper; their availability depends on the local installation. Source: claims_register.csv; README.md; desktop launchers.
Glossary and viva
Tap any viva question to reveal a short answer.
ADC Analog-to-digital converter: converts sampled voltage into numbers.
Bias A set operating voltage or current that places a device in a useful regime.
Cadence Virtuoso Circuit design environment used for the schematic flow.
Capacitance Ability to store electric charge; loading can delay an edge.
Circuit netlist A text description of components, connections and models.
Clock A recurring timing signal used to coordinate events.
CML Current-mode logic, which steers current through differential branches.
Complement An output with the opposite logical polarity.
Corner A selected combination of model and environmental conditions.
Cycle One complete repetition of a periodic signal.
Delay Elapsed time between specified events.
Differential Using a pair of signals whose difference carries information.
Divider A circuit whose output frequency is a fraction of its input frequency.
Duty cycle Fraction of a clock period spent at its high level.
E3 Preregistered test of the empirical load-onset estimate.
E6 Preregistered test of the delay-based equal-spacing prediction.
E7 Frequency refinement near observed division failure.
Edge A transition of a signal between levels.
FPGA Field-programmable gate array, a configurable digital device.
Frequency Number of cycles per unit time.
GPDK045 The process design kit supplying the circuit models used here.
GHz Gigahertz, a unit of frequency.
Heuristic A practical estimate without a general proof.
Latch A circuit that stores a state and can pass data when enabled.
Level R A claim backed by re-derivation from retained nominal raw waveforms.
Level S A claim backed by archived run summaries, without individual raw waveforms.
Load The circuit element receiving a signal and influencing its behavior.
LVS Layout versus schematic: a connectivity comparison.
Mismatch Differences between nominally matching devices in a statistical model.
Mixer Circuit that combines signals to translate frequency.
Monte Carlo Repeated simulation with randomly varied modeled parameters.
Multiphase Having several signals at different positions in a cycle.
Nominal The selected reference operating condition.
On-resistance An approximate resistance of a conducting device.
Oscillation Repeated variation in time; oscillation alone does not prove correct division.
PDK Process design kit: models and design rules for a fabrication process.
Period Time for one complete cycle.
Phase Position within a repeating cycle.
Phase step Angular interval between adjacent sorted output edges.
PVT Process, voltage and temperature.
Regeneration Positive feedback that reinforces a circuit state.
Ring A chain whose output feeds back to its input.
Silicon A fabricated integrated circuit; no result is claimed here.
Spectre The circuit simulator used for the modeled results.
Swing Voltage difference between low and high signal levels.
TSV Tab-separated values: a simple table file.
Waveform A signal represented as a function of time.
Yield Fraction of a manufactured population meeting a specification; corner counts are not yield.
Viva practice
Why divide a clock?
To create a slower timing signal from a faster source.
What is a phase?
A signal’s position within its repeating cycle.
Why use several phases?
They can schedule staggered operations or set relative timing in radio and sampling systems.
Can a divider have the correct frequency but bad phase?
Yes. Frequency and relative edge placement are distinct checks.
Why use differential outputs?
A latch naturally provides opposite-polarity signals that add useful phase observations.
What is the role of a latch?
It holds and passes state under clock control.
What does a corner test prove?
Behavior at the chosen modeled settings, not statistical manufacturing yield.
What does mismatch change?
It makes nominally matching devices differ, which can disturb timing and startup.
Why are raw waveforms valuable?
An independent analyst can recompute edge and power measurements from them.
What is a pre-layout simulation?
A circuit simulation without extracted parasitics from a completed physical layout.
Does an FPGA emulate transistor physics?
No. This demonstration is digital and cannot validate analog device behavior.
What would make the research stronger?
Retained waveforms, sensitivity tests, physical extraction and eventual silicon measurements.
What is a cliff?
A sampled boundary near which the strict division test changes from pass to fail.
Is the best point a guaranteed range?
No. A sampled point does not establish continuous margin.
Honest limitations and open items
The study uses one modeled process, idealized clocks, fixed loads and plain resistors; a duty-cycle, load and startup sensitivity matrix is not shown. The layout is placement-only, with no completed extraction or LVS-clean claim. Cover cells remain an open layout item. E7 raw archives remain in the simulation environment, while repository summaries support Level S checks only. More generally, Level S rows cannot be independently reconstructed from individual archived waveforms. Some housekeeping items remain. Sources: manuscript_v2.tex; e7_register_notes.md; peer_review_v2_r2.md; PROGRESS.md.
Final reminder: a careful draft can document a negative result, but only evidence can establish how a fabricated circuit behaves.
End of the divider field guide.
Unsized-PVT summary (U8k): U8k divides in 26 of 45 corners. All 15 hot corners (125 °C) fail. Pass counts: -40 °C 15/15, 27 °C 11/15, 125 °C 0/15. Supply: 0.9 V 7/15, 1.0 V 9/15, 1.1 V 10/15. Source: results/gpdk045/final/pvt_summary_U8k_1p4.json.
